ECTI TRANSACTIONS ON COMPUTER INFORMATION TECHNOLOGYVolume 12, No. 02, Month NOVEMBER, Year 2018, Pages 90 - 97
Scalable hardware mechanism for partitioned circuits operation
Yusuke Katoh, Hironari Yoshiuchi, Yoshio Murata, Hironori Nakajo
Abstract Download PDFFor designing hardware with a high-level synthe-sis tool using a programming language such as C or Java, its large size of logic circuit makes it difficult
to implement the design in a single FPGA. In such a case, partitioning the logic circuit and implementing in multiple FPGAs is a commonly used approach.
We propose the Scalable Hardware Mechanism,which enables the operation of a partitioned circuit to prevent the degradation of clock frequency by min-
imizing its dependence on the usage and the type of FPGA. Our mechanism provides a reduced delay by the collective signal transmission with the parti-
tioned AES code generation circuit and the character string edit distance calculation circuit as partitioned circuits.Etc...
Circuit operation, Partitioned circuit, FPGA